USB

USB Interface

USB Introduction

The UDC (USB device controller) uses an xHCI-like DMA model. There are two types of ring. A ring is a circular queue of TRB data structures used to pass TRBs from a producer to a consumer. Two pointers — Enqueue and Dequeue — are associated with each ring to identify where the producer will enqueue the next TRB and where the consumer will dequeue the next TRB.

A continuous area in IRAM is allocated for data exchange with the UDC.

• Event Ring Segment Table: The Event Ring Segment Table Size (ERSTSZ) register value is the number of segments described by the Event Ring Segment Table. The Event Ring Segment Table Base Address (ERSTBA) register points to the address of the Event Ring Segment Table.
• Event Ring: Used by UDC to return status and results of commands and transfers to system software. The EVENTCONFIG register enables corresponding events. The TRB Type field of an Event TRB indicates which event caused it. The Event Ring is pointed to by the Event Ring Dequeue Pointer (ERDP) register.
• Device Context: Consists of EP Contexts for Outbound and Inbound EPs. Device Contexts are pointed to by the Device Context Base Address Pointer (DCBAP) register.
• Transfer Ring: Used to move data between system memory buffers and UDC endpoints. There are 2 independent Transfer Rings for EP0 and EP1/2/3/4. The Initialize EP0 Command sets the pointer to the Transfer Ring for EP0. The Config EP Command loads EP Context to configure EPs.
• Data Buffer: Actual storage for exchange data. The data buffer address is contained in the Data Buffer Pointer field of a TRB.
• Interrupt: NVIC IRQn: 145. The Interrupt Management Register (IMAN) enables interrupts.
• Doorbell: A mechanism that actively notifies the UDC of data transmission. The Doorbell register indicates which endpoint needs to act.

USB Main Features

• USB 2.0 Device-mode
  • Supports High Speed and Full Speed.
  • Supports Control, Bulk, and Interrupt transfer types.
  • Supports L1/L2 power saving modes for USB 2.0 port.
  • Supports 5 endpoints: EP0 supports Control Transfer; EP1/2/3/4 support Bulk and Interrupt Transfer.

Event Ring

A fundamental difference between an Event Ring and a Transfer Ring is that the UDC is the producer and system software is the consumer of Event TRBs. The UDC writes Event TRBs to the Event Ring and updates the Cycle bit in the TRBs to indicate the current position of the Enqueue Pointer to software.

Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to 1 and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring. If the Cycle bit of the Event TRB pointed to by the Dequeue Pointer equals CCS, the Event TRB is valid — software processes it and advances the Dequeue Pointer. If the Cycle bit does not equal CCS, software stops processing Event TRBs and waits for an interrupt from the UDC.

System software shall write the Event Ring Dequeue Pointer (ERDP) register to inform the UDC that it has completed processing Event TRBs up to and including the TRB referenced by the ERDP.

Transfer Ring

Transfers to and from UDC endpoints are defined using a Transfer Descriptor (TD), which consists of one or more Transfer Request Blocks (TRBs). TDs are managed through Transfer Rings that reside in system memory. A Chain flag in the TRB is used to identify TRBs that comprise a TD — the Chain flag is set in all but the last TRB of a TD. A TD may consist of a single TRB, in which case the Chain flag shall not be set.

A Transfer Ring exists for each active endpoint or stream declared by a UDC.

In the simplest case, software defines a Transfer Ring by allocating and initializing a memory buffer, then setting the Enqueue and Dequeue Pointers to the address of the buffer and writing it into the TRB Dequeue Pointer field of the associated Endpoint. A Transfer Ring is empty when the Enqueue Pointer equals the Dequeue Pointer.

Note: The Transfer Ring Enqueue and Dequeue Pointers are not accessible through physical device controller registers. They are logical entities maintained internally by both system software and the device controller.

After a Transfer Ring is initialized, TDs (comprised of one or more TRBs) may be placed on it.

Data Structures

PEI Bitmap

PEI (Physical EP ID) bitmap is used by software to ring doorbell and request commands. EP0’s PEI is 0, mapped to bit[0].

• OEP: Outbound EP (EP_In from Host perspective)
• IEP: Inbound EP (EP_Out from Host perspective)

Device Contexts

Device Contexts are pointed to by the Device Context Base Address Pointer (DCBAP) register. They consist of EP Contexts for Outbound and Inbound EPs.

The first EP Context is for Outbound Physical EP 1 (PEI == 2), followed by Inbound Physical EP 1 (PEI == 3). When allocating memory for Device Contexts, software shall guarantee that it can accommodate all Physical EPs it intends to use.

EP0 does not have a corresponding EP Context. Its DQPTR, DCS, and MPS are set using the Command Interface.

Endpoint Context

Notes:

• DQPTR and DCS are set by the Initialize EP0 command.
• MPS is set by the Update EP0 command.
• Other EPs are configured by the Config EP command, which makes the endpoint context configuration effective.

TRB

A Transfer Request Block (TRB) is a data structure constructed in memory by software to transfer a single physically contiguous block of data between system memory and the UDC. TRBs contain a Data Buffer Pointer, the buffer size, and additional control information.

Transfer TRBs

Normal TRB

Control Data Stage TRB

Control Status Stage TRB

Event TRBs

Transfer Event TRB

Command Completion Event TRB

Port Status Change Event TRB

Setup Event TRB

Link TRB

Event Ring Segment TRB

TRB Fields

Control Bit Map

TRB Type Encoding

Completion Code Encoding

Command Interface

Command Types

Issuing a Command

To issue a command, software shall set Command Parameters first, then write the Command Control Register to specify Command Type and assert the Command Active bit.

If the IOC bit is asserted when writing the Command Control Register, software can wait for a Command Completion Event, which is automatically generated by the UDC when the command completes. Otherwise, software should poll the Command Active bit until it is de-asserted.

Software shall not write to Command Control or Command Parameter registers while the Command Active bit is asserted.

Polling the Command Active bit (rather than setting IOC) is recommended for:

• Initialize EP0
• Update EP0 Config
• Set Address
• Reset Seqnum

Command Definitions

Completion Status for all commands is always Success unless noted otherwise. The EPs to operate on (Config EP, Set Halt, Clear Halt, Reset Seqnum, Stop EP, Set TR DQPTR) are identified by the PEI bitmap.

Initialize EP0

Resets EP0 logic and initializes its transfer ring DQPTR and DCS. Software shall not issue this command when Setup Event Generation is enabled.

Note: Before Setup Event Generation is enabled, received setup requests are stored internally. Stored setups are not affected by Initialize EP0.

Update EP0

Updates MPS for EP0.

Set Address

When receiving a Set Address setup request, software shall use this command to provide hardware the received device address before ringing the doorbell to complete the Status Stage. The UDC switches to the new address only if the Status Stage completes successfully.

Note: The device does not wait for the Status Stage to finish before completing this command. Success status does not guarantee the device will switch to the new address.

Config EP

Adds Physical EP(s). If an EP’s corresponding bit in the PEI bitmap is asserted, the device loads the EP context to configure that EP, initializing its MPS, MBS, Interval, DQPTR, DCS, Logical EP Number, etc.

Set Halt

Halts Physical EP(s). A Transfer Event with Completion Code Halted or Halted-Length Invalid is generated when an EP is halted.

Clear Halt

Clears the halted state of Physical EP(s).

Reset Seqnum

Resets the Seqnum of Physical EP(s).

Stop EP

Stops Physical EP(s). A Transfer Event with Completion Code Stopped or Stopped-Length Invalid is generated when an EP is stopped.

Set TR DQPTR

Requests Physical EP(s) to re-initialize transfer ring DQPTR and DCS using the value in the corresponding EP Context. Software shall only issue this command when the EP is stopped or halted.

Note: After Set TR DQPTR, the EP restarts from the beginning of the new TRB when the doorbell is rung. If ringing the doorbell to a stopped EP without Set TR DQPTR, the EP continues from where it stopped. For a halted EP, ringing the doorbell directly after Clear Halt without Set TR DQPTR is not allowed.

Operational Flow

Initializing UDC on Plug-in

Software is recommended to perform a Soft Reset before initializing the UDC. After power-on or soft reset, device termination is disabled by default. Software must perform the following sequence:

1. Allocate and initialize Device Context, and program the DCBAP register to point to it.
2. Initialize Event Ring(s):
   • Allocate and initialize the Event Ring Segment(s).
   • Allocate the Event Ring Segment Table (ERST); initialize ERST entries to point to and define the size of each Event Ring Segment.
   • Program ERSTSZ with the number of segments.
   • Program ERDP with the starting address of the first segment.
   • Program ERSTBA to point to the Event Ring Segment Table.
3. Set Run/Stop = 1 to start UDC. Wait for CCS assertion indicating connection is established.
4. Issue Initialize EP0 Command to initialize EP0 and set DQPTR & DCS.
5. Issue Update EP0 Command to set MPS to 64 (HS) or 8/16/32/64 (FS).
6. Enable Setup Event Generation.

Handling Setup Requests

Setup requests received from the USB host are reported to software via Setup Event. A Setup Tag is assigned by the UDC for each Setup Event generated. Software shall use the same Setup Tag value when preparing the corresponding Data/Status Stage TRBs.

On receiving a Setup Event, software shall generally:

1. Decode the setup request to determine if it can be supported:
   • If the request cannot be supported: prepare only a Status Stage TRB with Status == STALL (even if a Data Stage would normally be required).
   • If the request does not require a Data Stage: prepare a Status Stage TRB with Status == OKAY. For SET_ADDRESS, assert the “Set Addr” bit in the Status Stage TRB.
   • If the request requires a Data Stage: prepare a Data Stage TRB (optionally chained with Normal TRBs), then a Status Stage TRB with Status == OKAY.
2. Ring the doorbell.

For the following setup requests, software shall perform additional tasks before ringing the doorbell:

• SET_ADDRESS: Issue Set Address Command to provide the UDC with the new device address.
• SET_CONFIGURATION / SET_INTERFACE: Drop EPs first, then add EPs.
  • To add EPs: allocate a Physical EP ID for each EP to add; re-initialize EP Context structures; issue Config EP command.
  • To drop EPs: look up the Physical EP ID by Logical Endpoint Number and direction; write 1s to the corresponding EP Enabled register bits to disable EPs.
• SET_FEATURE(EP_HALT): Issue Set Halt Command to halt the target EP.
• CLEAR_FEATURE(EP_HALT): Issue Reset Seqnum Command, then Clear Halt Command, then Set TR DQPTR Command.

Completion Events are generated by the UDC when TRBs with IOC set are completed, or when short packet or error conditions occur. Possible Completion Codes:

• Success: TD completed normally. If Status == STALL was set in a Status Stage TRB, Completion Code will be STALL.
• Short Packet (Inbound Data Stage TRB only): Host sent less data than the TD size. TRB Transfer Length indicates bytes not yet transferred. Device advances to next TD automatically; Transfer Event generated for IOC TRBs while advancing.
• Setup Tag Mismatch Error: UDC terminated current TD due to a new setup request. TRB Transfer Length indicates bytes not yet transferred. Device advances to next TD automatically.
• Protocol Stall Error: Unexpected protocol error (e.g. host requested more data than expected). EP0 transitions to EP0-Stall state; a subsequent setup request returns it to EP0-Running state.
• Disabled Error: Link down with pending transfers. TRB Transfer Length indicates bytes not yet transferred.

Handling Bulk and Interrupt Transfers

For Bulk and Interrupt EPs, TDs consist of Normal TRBs and optional Link TRBs. After preparing TDs, software rings the doorbell to notify the UDC.

Completion Events are generated when TRBs with IOC set are completed, or when short packet or error conditions occur. Possible Completion Codes:

• Success: TD completed successfully. If IOC is set on a Link TRB, Completion Code is always Success.
• Short Packet (Inbound EP only): Host sent less data than the TD size. TRB Transfer Length indicates bytes not yet transferred. Device advances to next TD automatically.
• Stopped: EP stopped by Stop EP Command with pending transfers. TRB Transfer Length indicates bytes not yet transferred.
• Stopped — Length Invalid: EP stopped by Stop EP Command with empty transfer ring.
• Halted: EP halted by Set Halt Command with pending transfers. TRB Transfer Length indicates bytes not yet transferred.
• Halted — Length Invalid: EP halted by Set Halt Command with empty transfer ring.
• Disabled Error: Link down with pending transfers. TRB Transfer Length indicates bytes not yet transferred.

Handling Disconnection

CCS de-assertion indicates the previously established connection is down (port reset or non-recoverable link error). On detecting CCS de-assertion, software shall:

1. If previous and current CCS status are both 1 but CSC is asserted, set software flag CHECK_PORTSC_AFTERWARDS.
2. Wait until the Controller Idle bit is asserted (UDC typically idles within several µs after disconnection).
3. Write 1s to the EP Enabled register to disable all enabled EPs.
4. Clean up all residual events in the Event Ring. If a Port Status Change Event is received, set CHECK_PORTSC_AFTERWARDS and continue.
5. If the device is not plugged out:
   • If CHECK_PORTSC_AFTERWARDS is set, immediately read PORTSC and check for CCS assertion.
   • If not set, or CCS assertion not detected, wait for CCS assertion, then follow the connection initialization sequence.
6. If the device is plugged out:
   • If powering down: do nothing.
   • Otherwise: follow the connection initialization sequence.

Notes:

• Setup Event Generation is automatically disabled when CCS is de-asserted.
• Device address is automatically reset to 0 when CCS is de-asserted.

USB Registers

Base address: 0x5020_2400

Register Descriptions

DEVCAP — Device Capability Register

• Address offset: 0x0000
• Access: RO

DEVCONFIG — Device Configuration Register

• Address offset: 0x0010
• Reset value: 0x0000_0000

EVENTCONFIG — Event Configuration Register

• Address offset: 0x0014
• Reset value: 0x0000_0000

USBCMD — USB Command Register

• Address offset: 0x0020
• Reset value: 0x0000_0000

USBSTS — USB Status Register

• Address offset: 0x0024
• Reset value: 0x0000_0000

DCBAP — Device Context Base Address Pointer

• Address offset: 0x0028 (Lo), 0x002C (Hi)
• Reset value: 0x0000_0000

PORTSC — Port Status and Control Register

• Address offset: 0x0030
• Reset value: 0x0000_0000

DOORBELL — Doorbell Register

• Address offset: 0x0040
• Reset value: 0x0000_0000

EPENABLE — EP Enabled Register

• Address offset: 0x0060
• Reset value: 0x0000_0000

EPRUNNING — EP Running Register

• Address offset: 0x0064
• Reset value: 0x0000_0000

CMDPARA0 — Command Parameter 0 Register

• Address offset: 0x0070
• Reset value: 0x0000_0000

CMDPARA1 — Command Parameter 1 Register

• Address offset: 0x0074
• Reset value: 0x0000_0000

CMDCTRL — Command Control Register

• Address offset: 0x0078
• Reset value: 0x0000_0000

IMAN — Interrupt Management Register

• Address offset: 0x0100 + (32 × Interrupter) where Interrupter = 0–3
• Reset value: 0x0000_0000

IMOD — Interrupter Moderation Register

• Address offset: 0x0104 + (32 × Interrupter) where Interrupter = 0–3
• Reset value: 0x0000_0000

ERSTSZ — Event Ring Segment Table Size Register

• Address offset: 0x0108
• Reset value: 0x0000_0000

ERSTBA — Event Ring Segment Table Base Address Register

• Address offset: 0x0110 (Lo), 0x0114 (Hi)
• Reset value: 0x0000_0000

ERDP — Event Ring Dequeue Pointer Register

• Address offset: 0x0118 (Lo), 0x011C (Hi)
• Reset value: 0x0000_0000