Power Management Unit - PMU

I/O Connections

VDD inputs:

• PMU (2.7 V – 3.6 V): VDD33
• I/O (3.3 V / 1.8 V):
  • VDD33_BCPAD, VDD33_DPAD, VDD33_QFCPAD: tied to VDDIO in package
  • VDD33_AOPAD, VDD33_TESTPAD, VDD33_EPAD, VDD33_APAD: tied to VDD33 in package.
• RRAM (2.7 V – 3.6 V): VDDRR0, VDDRR1: tied to VDD33R on stand-alone ball
• USB:
  • USBVCC33 (2.7 V – 3.6 V) tied to VDD33 in package
  • USBVCCCORE (0.80 V) - tied to VDD85 in package
• PLL:
  • PLL25VPAD (2.5 V) - Tied to VDD25 ball
  • PLL09VPAD (0.80 V) - tied to VDD85 in package
• ADC: ADCAVDD (2.5 V) - Tied to VDD25 ball

VDD outputs:

• VDD85D, VDD85A - ganged to VDD85 inside package
• VDDAO
• ANA_VDD25A tied to PLL25VPAD, ADCAVDD 2.5V

GND:

• All grounds ganged together in package
  • VSS, DVSS, VSSA
  • VSSPLL
  • ADCAVSS

Power Pad Description

Ground Pad Description

All ground pads tied to common GND bus in package.

I/O Power Domain Groups

There are two I/O power domains. One is fixed at 3.3V (tied to VDD33 internally), and the other is tied to VDDIO.

There are more I/Os on the die than are broken out in the CSP package due to ball count limitation on the package type. For higher-I/O count devices, please consult with Crossbar for an alternative, high-pin count BGA packaged device.

Below is the raw chip floorplan showing the location of the I/O power domains on-die. The power is further routed through an RDL (redistribution layer) and broken out to a limited number of CSP balls.

Power Timing Sequence

The following diagram shows the recommended power-on sequence for VDD33(I/O) and VDD33:

• VDD33(I/O): VDD33_APAD, VDD33_BCPAD, VDD33_DPAD, VDD33_EPAD, VDD33_AOPAD, VDD33_QFCPAD, VDD33_TESTPAD
• VDD33: VDD33, VDDRR0, VDDRR1, USBVCC33

• Stand-alone VDDIO may rise after VDD33 as the internal VDD33-bound I/O are tied to VDD33 and guaranteed to be valid on VDD33 rise.
• t2 should be >0.

Power Modes

Besides the regular active mode, the device provides three reduced power modes:

• Sleep mode
• Power-down mode

The following modes are listed from maximum to minimum power consumption.

Active Mode

In active mode, all clocks to the CPU cores, memories, and peripherals are enabled. The chip enters active mode after reset, with default power trimming determined by the ReRAM IFR power-on initialization. Power and clocks to selected peripherals and crypto engines can be optimized during runtime. All low-power modes can be entered from active mode.

Sleep Mode

In sleep mode, all clocks to the CPU cores are stopped and instruction execution is suspended until a reset or interrupt occurs. Selected functional blocks (peripherals, crypto engines) can continue operating at normal or reduced frequency and may generate interrupts as wake-up sources. SRAM contents are retained in sleep mode.

Entering sleep mode:

Sleep mode is entered by executing a WFI instruction after optionally configuring lower-frequency clock settings. Crypto engines, peripherals, and memories remain operational.

Waking up from sleep mode:

Any interrupt or RESET wakes the device from sleep mode. GPIO interrupts and selected peripherals (SPI, I2C, etc.) can serve as wake-up sources. The chip resumes using the same power configuration it had before sleep.

Power-Down Mode

In power-down mode, all clocks, the CPU core, and all functional blocks are powered down except the always-on (AO) domain. External power supplies remain on. Most SRAM and register contents are not retained — only AO SRAMs and AO backup registers are preserved.

Entering power-down mode:

Configure AO wake-up sources, then write 0x0000_005A to the PMU_PDAR register. The SoC power domain shuts off; only the AO domain remains powered.

Waking up from power-down mode:

Wake-up from power-down is triggered by asserting RESET, or by asserting PF0 or PF1 pins. On wake-up, the PMU powers on the SoC domain, the ReRAM IFR is re-read, RAMs reset to zero, and the CPU restarts from the beginning. Backup-registers, RTC and AORAM in the AO domain are preserved if the wake-up source is from the PF pins; if external reset is used, then these registers are cleared.

Low-Power Mode Summary

These modes should be activated using the low-power mode library API from the SDK software package. Power usage is primarily controlled by CGU clock settings, PMU regulator settings, and the CPU operating mode.

Low-Power Control API Reference Flow

Enter Sleep Mode

1. (Optional) Configure PMU_CRLP and PMU_TRMLP* registers with reduced power settings and trimmings for sleep entry.
2. (Optional) Configure CGUFD_* registers (0x4004_0014 – 0x4004_003C) with reduced clock frequencies for sleep entry.
3. (Optional) Write 0x3 to CGULP (0x4004_0004) to enable low-power frequency division and disable OSC/PLL on sleep entry.
4. Configure and enable wake-up sources.
5. Execute WFI / WFE instruction — CPU core clocks stop.
6. Device remains in sleep mode until a valid wake-up source triggers.
7. On wake-up, the CPU resumes execution from the next instruction.

As of Xous 0.10.1, the above sequence is already implemented and accessible via an API call to enter suspend via the Suspend/Resume manager:

    let xns = xous_names::XousNames::new().unwrap();
    let susres = susres::Susres::new_without_hook(&xns).unwrap();
    susres.initiate_suspend().unwrap();

To access the xous_names and susres APIs, you will need this in your Cargo.toml:

   susres = { package = "xous-api-susres", version = "0.9.68" }
   xous-names = { package = "xous-api-names", version = "0.9.71" }

Enter Power-Down Mode

1. (Optional) Configure PMU_CRPD register with power-down settings.
2. (Optional) Store any important data to AO backup registers or AORAM before entry.
3. Configure and enable AO wake-up sources.
4. Write 0x0000_005A to PMU_PDAR — all SoC domain blocks shut off; only the AO domain remains powered.
5. Device remains in power-down until a valid AO wake-up source triggers.
6. On wake-up, the PMU powers on the SoC domain. The ReRAM IFR is re-read, RAMs reset to zero, and the CPU restarts from the beginning.

As of Xous 0.10.1, the above sequence is already implemented via an API call to enter power-down mode that requires a PlatformSpecific call:

    use num_traits::ToPrimitive;

    let xns = xous_names::XousNames::new().unwrap();
    let susres_conn =
        xns.request_connection_blocking(susres::api::SERVER_NAME_SUSRES).expect("Can't connect to SUSRES");
    xous::send_message(
        susres_conn,
        xous::Message::new_scalar(
            susres::api::Opcode::PlatformSpecific.to_usize().unwrap(),
            bao1x_hal::ClockOp::DeepSleep.to_usize().unwrap(),
            0,
            0,
            0,
        ),
    )
    .ok();

You’ll need these crates to make the above call:

   xous = "0.9.70"
   susres = { package = "xous-api-susres", version = "0.9.68" }
   xous-names = { package = "xous-api-names", version = "0.9.71" }
   bao1x-hal = { features = [
       "std",
   ], git = "https://github.com/betrusted-io/xous-core", branch = "dev" }
   num-traits = { version = "0.2.14", default-features = false }

PMU Regulator and Trim Block

PMU Introduction

• 2.5 V Regulator (VR25): 2.55 V regulator powered from VDD. Supports power-down enable and ready status indication.
• 0.85 V Regulators for Analog/Digital (VRCOREA, VRCORED): 0.85 V regulators powered from VDD. Support power-down enable, ready status indication, and overshoot enable.
• 0.8 V Always-On Regulator (VRAO): 0.77 V regulator powered from VDD.
• Current Source Output (IOUT): Provides several current sources, including a 10 µA output to a test pin for calibration against an external resistor (enabling absolute-value accuracy rather than tracking integrated resistors).
• Power On/Down Reset (PORPDR): Provides power-on reset signal. Also triggers when power drops low enough to lose the always-on regulator.
• Bandgap (BG): Ready status indication. The 1.5 V (VOUT1P5), 1.2 V (VOUT1P2), and 0.6 V (VOUTP60) references are individually trimmable. CTAT and PTAT currents are trimmable.

PMU Main Features

• Provides regulated supplies: VDD25, VDD85A, VDD85D, VDDAO.
• Generates power-on and power-down reset signals.
• Supports power-down mode.

PMU & AO Control Registers

Base address: 0x4006_0000

Register Descriptions

AO_CLK32K_SEL — AO 32 kHz Clock Source Selection

• Address offset: 0x0000
• Reset value: 0x0000_0006

AO_CLK1HZ_FD — 1 Hz Clock Frequency Divider

• Address offset: 0x0004
• Reset value: 0x0000_3FFF

AO_WKUP_INTEN — Wakeup Mask and Interrupt Enable

• Address offset: 0x0008
• Reset value: 0x0000_0000

Interrupt enable bits (0 = disabled, 1 = enabled):

Wakeup mask bits (0 = source can wake system, 1 = source cannot wake system):

AO_RSTCR_MASK — Reset Mask Control Register

• Address offset: 0x000C
• Reset value: 0x0000_001F

Each bit masks a reset source (0 = source can reset system, 1 = source cannot reset system):

PMU_CR — PMU Block Control Register (Active Mode)

• Address offset: 0x0010
• Reset value: 0x0000_007C

PMU_CRLP — PMU Block Control Register (Sleep / Deep-Sleep)

• Address offset: 0x0014
• Reset value: 0x0000_007C

Same bit definition as PMU_CR. These are separate configuration values applied when entering sleep or deep-sleep mode.

PMU_CRPD — PMU Block Control Register (Power-Down)

• Address offset: 0x0018
• Reset value: 0x0000_007C

Same bit definition as PMU_CR. These are separate configuration values applied when entering power-down mode.

PMU_DFT — PMU Default Test Register

• Address offset: 0x001C
• Reset value: 0x0000_0002

PMU_TRM0 — PMU Trimming Low 32-bit Register (Active Mode)

• Address offset: 0x0020
• Reset value: 0x0842_1080

PMU_TRM1 — PMU Trimming High 32-bit Register (Active Mode)

• Address offset: 0x0024
• Reset value: 0x0000_0002

PMU_TRMLP0 — PMU Trimming Low 32-bit Register (Low-Power)

• Address offset: 0x0028
• Reset value: 0x0842_1080

Same bit definition as PMU_TRM0. Applied during sleep and deep-sleep mode.

PMU_TRMLP1 — PMU Trimming High 32-bit Register (Low-Power)

• Address offset: 0x002C
• Reset value: 0x0000_001F

Same bit definition as PMU_TRM1. Applied during sleep and deep-sleep mode.

AO_OSC_CR — AO 32 kHz Oscillator Control Register

• Address offset: 0x0034
• Reset value: 0x0001_2D2D

PMU_SR — PMU Ready Status Register

• Address offset: 0x0038
• Reset value: 0x0000_001F
• Access: Read-only (real-time status)

PMU_FR — PMU Error Flag Register

• Address offset: 0x003C
• Reset value: 0x0000_0000

Bits are set if the corresponding supply was below its threshold after power-on. Write 1 to a bit to clear it.

AO_FR — AO Domain Interrupt Flag Register

• Address offset: 0x0040
• Reset value: 0x0000_0000

Write 1 to a bit to clear it.

PMU_PDAR — Power-Down Activation Register

• Address offset: 0x0044
• Type: AR (action register)
• Reset value: 0x0000_0000 (always reads zero)

AO_PERI_CLR — Wakeup Interrupt Clear Register

• Address offset: 0x0050
• Type: AR (action register, always reads zero)

AO_IOX — Port F Alternate Function Selection Register

• Address offset: 0x0060
• Reset value: 0x0000_0000

Note: Use AO_IOX to configure Port F alternate function selection. The AFSEL registers for Port F (0x5012_F028, 0x5012_F02C) are not used.

AO_PADPU — Port F Pull-Up Configuration Register

• Address offset: 0x0064
• Reset value: 0x0000_03FF (all pull-ups enabled by default)

Each bit controls pull-up for the corresponding Port F pin (0 = floating when undriven, 1 = weak pull-up when undriven):

Note: Use AO_PADPU to configure Port F pull-ups. The GPIOPU register for Port F (0x5012_F174) is not used.

VDD85 Trim Table